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ltc3412a 1 3412afc applicatio s u descriptio u features typical applicatio u point-of-load regulation notebook computers portable instruments distributed power systems high ef? ciency: up to 95% 3a output current low quiescent current: 64a low r ds(on) internal switch: 77m 2.25v to 5.5v input voltage range programmable frequency: 300khz to 4mhz 2% output voltage accuracy 0.8v reference allows low output voltage selectable forced continuous/burst mode ? operation with adjustable burst clamp synchronizable switching frequency low dropout operation: 100% duty cycle power good output voltage monitor overtemperature protected available in 16-lead exposed pad tssop and qfn packages 3a, 4mhz, monolithic synchronous step-down regulator the ltc ? 3412a is a high ef? ciency monolithic synchro- nous, step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.25v to 5.5v and provides a regulated output voltage from 0.8v to 5v while deliver- ing up to 3a of output current. the internal synchronous power switch with 77m on-resistance increases ef? ciency and eliminates the need for an external schottky diode. switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. opti-loop ? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the ltc3412a can be con? gured for either burst mode operation or forced continuous operation. forced continu- ous operation reduces noise and rf interference while burst mode operation provides high ef? ciency by reducing gate charge losses at light loads. in burst mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the application requirements. 3412a f01a sync/mode v fb pgood sw pgnd sgnd rt run/ss i th sv in pv in ltc3412a 294k 22f c out 100f 2 0.47h v out 2.5v at 3a v in 3.3v 1000pf 2.2m 820pf 12.1k 115k 69.8k 392k ef? ciency and power loss figure 1. 2.5v/3a step-down regulator load current (a) 0.01 efficiency (%) power loss (mw) 100 95 90 85 80 75 70 65 60 55 50 100000 10000 1000 100 10 1 0.1 1 10 3412a f01b efficiency power loss , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.
ltc3412a 2 3412afc input supply voltage .................................... ?0.3v to 6v i th , run/ss, v fb , pgood, sync/mode voltages ....................................?0.3 to v in sw voltages ..................................?0.3v to (v in + 0.3v) absolute axi u rati gs w ww u (note 1) operating ambient temperature range (note 2) ...............................................? 40c to 85c junction temperature (note 5) ............................. 125c lead temperature (soldering, 10 sec) .................. 300c t jmax = 125c, = = ( ) = = = ( ) ( ) ( ) ( ) ( ) ( )
ltc3412a 3 3412afc electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise speci? ed. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3412ae is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3412ai is guaranteed to meet performance speci? cations over the full C40c to 85c operating temperature range. note 3: the ltc3412a is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and power dissipation as follows: ltc3412afe: t j = t a + p d (38c/w) ltc3412auf: t j = t a + p d (34c/w) note 6: 4mhz operation is guaranteed by design and not production tested. note 7: switch on resistance is guaranteed by design and test condition in the uf package and by ? nal test correlation in the fe package. symbol parameter conditions min typ max units sv in signal input voltage range 2.25 5.5 v v fb regulated feedback voltage (note 3) 0.784 0.800 0.816 v i fb voltage feedback leakage current 0.1 0.2 a v fb reference voltage line regulation v in = 2.7v to 5.5v (note 3) 0.04 0.2 %v v loadreg output voltage load regulation measured in servo loop, v ith = 0.36v measured in servo loop, v ith = 0.84v 0.02 C0.02 0.2 C0.2 % % v pgood power good range 7.5 9 % r pgood power good pull-down resistance 120 200 i q input dc bias current active current sleep shutdown (note 4) v fb = 0.78v, v ith = 1v v fb = 1v, v ith = 0v v run = 0v, v mode = 0v 250 64 0.02 330 80 1 a a a f osc switching frequency switching frequency range r osc = 294k (note 6) 0.88 0.3 1 1.1 4 mhz mhz f sync sync capture range (note 6) 0.3 4 mhz r pfet r ds(on) of p-channel fet i sw = 1a (note 7) 77 110 m r nfet r ds(on) of n-channel fet i sw = C1a (note 7) 65 90 m i limit peak current limit 4.5 6 a v uvlo undervoltage lockout threshold 1.75 2 2.25 v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 1 a v run run threshold 0.5 0.65 0.8 v i run run/ss leakage current 1a
ltc3412a 4 3412afc input voltage (v) 2.5 94 92 90 88 86 84 82 80 4.0 3412a go4 3.0 3.5 4.5 5.0 3412a go5 3412a go8 3412a go7 3412a go9 efficiency (%) load current (a) 0 v out /v out (%) 0 C0.1 C0.2 C0.3 C0.4 C0.5 C0.6 0.5 1.0 1.5 2.0 3412a go6 2.5 3.0 0.1a 1a 3a 5s/div 5s/div 40s/div v out 20mv/div inductor current 1a/div v out 100mv/div inductor current 2a/div forced continuous 20mv/div pulse skipping 20mv/div burst mode 20mv/div v in = 3.3v v out = 2.5v f = 1mhz load step = 50ma to 2a figure 4 circuit v in = 3.3v v out = 2.5v figure 4 circuit figure 4 circuit efficiency (%) 96 95 94 93 92 91 90 89 88 87 frequency (mhz) 0 4.0 1.0 2.0 3.0 0.5 1.5 2.5 3.5 0.22h 0.47h 1h figure 4 circuit v in = 3.3v figure 4 circuit figure 4 circuit v in = 3.3v typical perfor a ce characteristics uw burst mode operation load step transient burst mode operation ef? ciency vs input voltage ef? ciency vs frequency load regulation output voltage ripple ef? ciency vs load current ef? ciency vs load current, burst mode operation ef? ciency vs load current, forced continuous operation load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 0.1 1 10 load current (a) 0.01 0.1 1 10 load current (a) 0.01 0.1 1 10 3412a go1 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 3412a go2 3412a go3 burst mode operation forced continuous v in = 3.3v v in = 3.3v v out = 2.5v figure 4 circuit v out = 2.5v figure 4 circuit v out = 2.5v figure 4 circuit v in = 5v v in = 3.3v v in = 5v
ltc3412a 5 3412afc input voltage (v) 2.5 on-resistance (m) 100 95 90 85 80 75 70 65 60 55 50 4.5 3412a g13 3.0 3.5 4.0 5.0 2.5 4.5 3.0 3.5 4.0 5.5 5.0 3412a g10 3412a g11 temperature (c) on-resistance (m) 3412a g14 120 100 80 60 40 20 0 C40 0 40 60 C20 20 80 100 120 input voltage (v) 2.5 switch leakage current (na) 3.0 3.5 4.0 4.5 3412a g15 5.0 50 45 40 35 30 25 20 15 10 5 0 5.5 r osc (k) 40 frequency (khz) 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 240 440 540 940 3412a g16 140 340 640 740 840 input voltage (v) frequency (khz) 1060 1050 1040 1030 1020 1010 1000 990 3412a g17 temperature (c) C40 frequency (khz) 1020 1015 1010 1005 1000 995 990 985 980 975 970 0 40 60 3412a g18 C20 20 80 100 120 temperature (c) C45 v ref (v) 75 0.7975 0.7970 0.7965 0.7960 0.7955 0.7950 0.7945 0.7940 0.7935 0.7930 3412a g12 C25 C5 15 35 55 95 115 40s/div 1ms/div v out 100mv/div v out 2v/div run/ss 2v/div inductor current 2a/div inductor current 2a/div v in = 3.3v v out =2.5v f = 1mhz load step = 0a to 3a figure 4 circuit v in = 3.3v v out =2.5v load step = 2a figure 4 circuit pfet pfet pfet nfet nfet nfet v in = 3.3v v in = 3.3v v in = 3.3v r osc = 294k v in = 3.3v r osc = 294k typical perfor a ce characteristics uw start-up transient switch on-resistance vs temperature switch leakage current vs input voltage switch on-resistance vs input voltage frequency vs r osc frequency vs input voltage frequency vs temperature v ref vs temperature load step transient forced continuous
ltc3412a 6 3412afc quiescent current vs temperature minimum peak inductor current vs burst clamp voltage quiescent current vs input voltage typical perfor a ce characteristics uw input voltage (v) quiescent current (a) 350 300 250 200 150 100 50 0 3412a g19 quiescent current (a) 350 300 250 200 150 100 50 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 temperature (c) C40 80 3412a g20 0 40 120 C20 20 60 100 v burst (v) 0.1 0.2 maximum peak inductor current (ma) 0.3 0.5 0.4 0.6 0.7 3412a g21 4000 3500 3000 2500 2000 1500 1000 500 0 input voltage (v) 2.25 2.75 peak inductor current (a) 3.25 4.25 3.75 4.75 3412a g22 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 active sleep active sleep v in = 3.3v peak current vs input voltage
ltc3412a 7 3412afc sv in (pin 1/pin 11): signal input supply. decouple this pin to sgnd with a capacitor. pgood (pin 2/pin 12): power good output. open-drain logic output that is pulled to ground when the output volt- age is not within 7.5% of regulation point. i th (pin 3/pin 13): error ampli? er compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.4v corresponding to the zero-sense voltage (zero current). v fb (pin 4/pin 14): feedback pin. receives the feedback voltage from a resistive divider connected across the output. r t (pin 5/pin 15): oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. sync/mode (pin 6/pin 16): mode select and external clock synchronization input. to select forced continuous, tie to sv in . connecting this pin to a voltage between 0v and 1v selects burst mode operation with the burst clamp set to the pin voltage. uu u pi fu ctio s run/ss (pin 7/pin 1): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3412a. in shutdown all functions are disabled drawing < 1a of supply current. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 8/pin 2): signal ground. all small-signal com- ponents, compensation components and the exposed pad on the bottom side of the ic should connect to this ground, which in turn connects to pgnd at one point. pv in (pins 9, 16/pins 3, 10): power input supply. decouple this pin to pgnd with a capacitor. sw (pins 10, 11, 14, 15/pins 4, 5, 8, 9): switch node connection to the inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. pgnd (pins 12, 13/pins 6, 7): power ground. connect this pin close to the (C) terminal of c in and c out . exposed pad (pin 17/pin 17): signal ground. must be soldered to pcb for electrical connection and rated thermal performance. (fe package/uhf package)
ltc3412a 8 3412afc main control loop the ltc3412a is a monolithic, constant-frequency, current- mode step-down dc/dc converter. during normal opera- tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error ampli? er adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error ampli? er raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C1.3a for forced continuous mode and 0a for burst mode operation. operatio u ? + 2 7 4 ? + + ? ? + 0.74v error amplifier sync/mode burst comparator bclamp nmos current comparator pmos current comparator reverse current comparator 0.86v run run/ss 15 13 12 14 11 sw p-ch n-ch 10 pgood 3 i th v fb 0.8v 5 r t 6 sync/mode 3412 fbd 16 pv in 9 8 sgnd 1 sv in slope compensation voltage reference oscillator logic slope compensation recovery ? + ? + + ? pgnd + ? fu n ctio n al block diagra uu w
ltc3412a 9 3412afc the operating frequency is externally set by an external resistor connected between the rt pin and ground. the practical switching frequency can range from 300khz to 4mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. forced continuous mode connecting the sync/mode pin to sv in will disable burst mode operation and force continuous current operation. at light loads, forced continuous mode operation is less ef? cient than burst mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. the output voltage ripple is minimized in this mode. burst mode operation connecting the sync/mode pin to a voltage in the range of 0v to 1v enables burst mode operation. in burst mode operation, the internal power mosfets operate intermit- tently at light loads. this increases ef? ciency by minimiz- ing switching losses. during burst mode operation, the minimum peak inductor current is externally set by the voltage on the sync/mode pin and the voltage on the i th pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the i th pin drops. as the i th voltage falls below 150mv, the burst comparator trips and enables sleep mode. during sleep mode, the top power mosfet is held off and the i th pin is disconnected from the output of the error ampli? er. the majority of the internal circuitry is also turned off to reduce the quiescent current to 64a while the load current is solely supplied by the output capacitor. when the output voltage drops, the i th pin is reconnected to the output of the error ampli? er and the top power mosfet along with all the internal circuitry is switched back on. this process repeats at a rate that is dependent on the load demand. pulse skipping operation is implemented by connecting the sync/mode pin to ground. this forces the burst clamp level to be at 0v. as the load current decreases, the peak inductor current will be determined by the voltage on the i th pin until the i th voltage drops below 400mv. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. frequency synchronization the internal oscillator of the ltc3412a can be synchro- nized to an external clock connected to the sync/mode pin. the frequency of the external clock can be in the range of 300khz to 4mhz. for this application, the oscil- lator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. during synchronization, the burst clamp is set to 0v, and each switching cycle begins at the falling edge of the clock signal. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3412a is designed to operate down to an input supply voltage of 2.25v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3412a is used at 100% duty cycle with low input volt- ages to ensure that thermal limits are not exceeded. operatio u
ltc3412a 10 3412afc slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3412a, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. this keeps the maximum output current relatively constant regardless of duty cycle. short-circuit protection when the output is shorted to ground, the inductor cur- rent decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases larger than 4.4a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. the basic ltc3412a application circuit is shown in fig- ure 1. external component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3412a is determined by an external resistor that is connected between pin r t and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r osc = 3.08 ? 10 11 f () ?10k although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3412a imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns; therefore, the minimum duty cycle is equal to 100 ? 110ns ? f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in or v out and decreases with higher inductance. i l = v out fl 1? v out v in having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors, and the output voltage ripple. highest ef? ciency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l = v out f i l(max) 1? v out v in(max) the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. applicatio s i for atio wu uu
ltc3412a 11 3412afc ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price verus size requirements and any radiated ? eld/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko, and sumida. c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoidal wave current at the source of the top mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms = i out(max) v out v in v in v out ?1 this formula has a maximum at v in = 2v out , where i rms = i out/2 . this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, suf? cient bulk input capacitance is needed to minimize transient effects during output load changes. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: v out i l esr + 1 8fc out the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coef? cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signi? cant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. applicatio s i for atio wu uu
ltc3412a 12 3412afc output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.8v 1 + r2 r1 the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 2. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple increase. the burst clamp voltage, v burst , can be set by a resistor divider from the v fb pin to the sgnd pin as shown in figure 1. pulse skipping, which is a compromise between low out- put voltage ripple and ef? ciency, can be implemented by connecting pin sync/modeto ground. this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator. the lowest output voltage ripple is achieved while still operat- ing discontinuously. during very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. frequency synchronization the ltc3412as internal oscillator can be synchronized to an external clock signal. during synchronization, the top mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 4mhz. synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. because slope compensation is generated by the oscillators rc circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. soft-start the run/ss pin provides a means to shut down the ltc3412a as well as a timer for soft-start. pulling the run/ss pin below 0.5v places the ltc3412a in a low quiescent current shutdown state (i q < 1a). the ltc3412a contains an internal soft-start clamp that gradually raises the clamp on i th after the run/ss pin is pulled above 2v. the full current range becomes available on i th after 1024 switching cycles. if a longer soft-start period is desired, the clamp on i th can be set externally with a resistor and capacitor on the run/ss pin as shown in figure 1. the soft-start duration can be calculated by using the following formula: t ss = r ss c ss ln v in v in ? 1.8v (seconds) applicatio s i for atio wu uu 3412a f02 ltc3412a v fb sgnd v out r2 r1 figure 2. setting the output voltage burst clamp programming if the voltage on the sync/mode pin is less than v in by 1v, burst mode operation is enabled. during burst mode operation, the voltage on the sync/mode pin determines the burst clamp level, which sets the minimum peak inductor current, i burst . to select the burst clamp level, use the graph of minimum peak inductor current vs burst clamp voltage in the typical performance characteristics section. v burst is the voltage on the sync/mode pin. i burst can only be programmed in the range of 0a to 6a. for values of v burst greater than 1v, i burst is set at 6a. for values of v burst less than 0.4v, i burst is set at 0a. as the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the i th pin will decrease. when the i th voltage drops to 150mv, sleep mode is enabled in which both power mosfets are shut off along with most of the circuitry to minimize power consumption. all circuitry is turned back on and the power mosfets begin switching again when the output voltage drops out of regulation.
ltc3412a 13 3412afc ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the ef? ciency loss at very low load currents whereas the i 2 r loss dominates the ef? ciency loss at medium to high load currents. in a typical ef? ciency plot, the ef? ciency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteris- tics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(qt + qb) where qt and qb are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in ; thus, their effects will be more pro- nounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in con- tinuous mode the average output current ? owing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3412a does not dissipate much heat due to its high ef? ciency. however, in applications where the ltc3412a is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3412a from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. for the 16-lead exposed tssop package, the ja is 38c/w. for the 16-lead qfn package the ja is 34c/w. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). to maximize the thermal performance of the ltc3412a, the exposed pad should be soldered to a ground plane. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. applicatio s i for atio wu uu
ltc3412a 14 3412afc when a load step occurs, v out immediately shifts by an amount equal to i load(esr) , where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components and output capacitor shown in figure 1 will provide adequate compensation for most applications. design example as a design example, consider using the ltc3412a in an application with the following speci? cations: v in = 3.3v, v out = 2.5v, i out(max) = 3a, i out(min) = 100ma, f = 1mhz. because ef? ciency is important at both high and low load current, burst mode operation will be utilized. first, calculate the timing resistor: rkk osc == 308 10 110 10 298 11 6 .? ? ? use a standard value of 294k. next, calculate the inductor value for about 40% ripple current at maximum v in : l = 2.5v (1mhz)(1.2a) 1C 2.5v 3.3v = 0.51 h using a 0.47h inductor results in a maximum ripple current of: i l = 2.5v (1mhz)(0.47 h) 1C 2.5v 3.3v = 1.29a sr . 100. i z i rms = (3a) 2.5v 3.3v 3.3v 2.5v C1 = 1.29a rms decoupling the pv in and sv in pins with two 22f capaci- tors is adequate for most applications. the burst clamp and output voltage can now be pro- grammed by choosing the values of r1, r2, and r3. the voltage on pin mode will be set to 0.50v by the resistor divider consisting of r2 and r3. according to the graph of minimum peak inductor current vs burst clamp volt- age in the typical performance characteristics section, a burst clamp voltage of 0.5v will set the minimum inductor current, i burst , to approximately 1.1a. if we set the sum of r2 and r3 to 185k, then the following equations can be solved: rr k r r v v 2 3 185 1 2 3 08 050 += += . . the two equations shown above result in the following values for r2 and r3: r2 = 69.8k , r3 = 115k. the value of r1 can now be determined by solving the following equation. 1 1 185 25 08 1 392 += = r k v v rk . . a value of 392k will be selected for r1. figure 4 shows the complete schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3412a. check the following in your layout: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3412a. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. applicatio s i for atio wu uu
ltc3412a 15 3412afc figure 4. 3.3v to 2.5v, 3a regulator at 1mhz, burst mode operation applicatio s i for atio wu uu figure 3. ltc3412a layout diagram 8 sgnd c ss 1000pf x7r c c 47pf * ** vishay ihlp-2525cz-01 tdk 4532x5r0j107m 7 r ss 2.2m run 6 sync/mode r osc 294k 5 r t r2 69.8k 4 r3 115k v fb r ith 17.4k 3 c ith 330pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412a efe 13 l1* 0.47h pgnd 14 sw 15 sw 16 pv in c in2 22f x5r 6.3v c in1 22f c out ** 100f 2 v out 2.5v 3a v in 3.3v gnd 3412 f04 r1 392k c in3 ** 100f r pg 100k c ff 22pf x5r top bottom 3. keep the switching node, sw, away from all sensitive small signal nodes. 4. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd, or any other dc rail in your system). 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd.
ltc3412a 16 3412afc typical applicatio s u 1.2v, 3a, 1.5mhz 1mm height regulator using all ceramic capacitors 1.8v, 3a step-down regulator at 1mhz, burst mode operation 2 sgnd c ss 1000pf x7r 1 r ss 2.2m run 16 sync/mode r osc 196k 15 r t r2 187k 14 v fb r ith 6.34k 13 c ith 1000pf x7r i th 12 pgood pgood 11 sv in 3 pv in 4 sw 5 sw 6 pgnd ltc3412a euf 7 l1* 0.47h pgnd 8 sw 9 sw 10 pv in c1 22pf x5r c in2 10f x5r 6.3v c in1 10f x5r 6.3v c out ** 22f x3 v out 1.2v 3a v in 3.3v gnd 3412 ta01 r1 95.3k * ** cooper sd10-r47 taiyo yuden amk212bj226md-b c c 22pf r pg 100k 8 sgnd c ss 1000pf x7r 7 r ss 2.2m run 6 sync/mode r osc 294k 5 r t r2 69.8k r3 115k 4 v fb r ith 15k 3 c ith 820pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412a efe 13 pgnd 14 sw 15 sw 16 pv in c in2 22f x5r 6.3v c in1 22f x5r 6.3v c out ** 100f 3 v out 1.8v 3a v in 2.5v gnd r1 232k 3412 ta02 l1 0.47h* * ** vishay ihlp-2525cz-01 tdk c4532x5r0j107m c2 47pf c1 47pf x5r r pg 100k c in3 ** 100f
ltc3412a 17 3412afc typical applicatio s u 3.3v, 3a step-down regulator at 2mhz, forced continuous mode operation 8 sgnd c ss 1000pf x7r 7 r ss 2.2m run 6 sync/mode r osc 137k 5 r t r2 200k 4 v fb r ith 7.5k 3 c ith 820pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412a efe 13 pgnd 14 sw 15 sw 16 pv in c in2 22f x5r 6.3v c in1 22f x5r 6.3v c out ** 100f 2 v out 3.3v 3a v in 5v gnd r1 634k 3412 ta03 l1* 0.47h * ** vishay ihlp-2525cz-01 tdk c4532x5r0j107m c c 47pf c1 22pf x5r c in3 ** 100f r pg 100k 2.5v, 3a step-down regulator synchronized to 1.8mhz 8 sgnd c ss 1000pf x7r 7 r ss 2.2m run 6 sync/mode 1.8mhz ext clock r osc 182k 5 r t r2 162k 4 v fb r ith 6.49k r pg 100k 3 c ith 220pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412a efe 13 l1* 0.47h pgnd 14 sw 15 sw 16 pv in c in2 22f x5r 6.3v c in1 22f x5r 6.3v c out ** 150f v out 1.5v 3a v in 3.3v gnd r1 392k 3412 ta04 * ** cooper sd20-r47 sanyo poscap 4tpe150mazb c c 22pf c1 22pf x5r +
ltc3412a 18 3412afc package descriptio u fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ba fe16 (ba) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3412a 19 3412afc package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uf package 16-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1692) 4.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wggc) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.55 0.20 16 15 1 2 bottom viewexposed pad 2.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.30 0.05 0.65 bsc 0.200 ref 0.00 C 0.05 (uf16) qfn 10-04 recommended solder pad pitch and dimensions 0.72 0.05 0.30 0.05 0.65 bsc 2.15 0.05 (4 sides) 2.90 0.05 4.35 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer
ltc3412a 20 3412afc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2005 lt 0708 rev c ? printed in usa related parts part number description comments ltc1878 600ma (i out ), 550khz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a i sd <1a, ms8 package ltc1879 1.20a (i out ), 550khz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 10v, v out(min) = 0.8v, i q = 15a, i sd <1a, tssop16 package lt1934/lt1934-1 300ma (i out ), constant off-time, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 3.2v to 34v, v out(min) = 1.25v, i q = 14a, i sd <1a, thinsot ? package ltc3404 600ma (i out ), 1.4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd <1a, ms8 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd <1a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd <1a, thinsot package ltc3407 dual 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, ms10e and 3mm 3mm dfn packages ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, ms10 and 3mm 3mm dfn packages ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, tssop16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% efficiency, v in : 2.25v to 5.5v, v out(min) = v ref/2 , i q = 280a, i sd <1a, tssop16e package ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop20e package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop20e package ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 380a, i sd <1a, qfn package lt3430 60v, 2.75a (i out ), 200khz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, i sd 25a, tssop16e package ltc3440 600ma (i out ), 2mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out : 2.5v to 5.5v, i q = 25a, i sd <1a, dfn package ltc3441 1.2a (i out ), 1mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 25a, i sd <1a, dfn package ltc3548 400ma/800ma dual synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q <40a, i sd <1a, ms8e and dfn packages thinsot is a trademark of linear technology corporation.

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